Serial Divider Using Modified GDI Technique

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique

Received Jan 15, 2015 Revised Jun 9, 2015 Accepted Jul 12, 2015 Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI (Gate Diffusion Input) Technique. Modified G...

متن کامل

Design of Self Calibrated DLL Based Clock Generator Using Modified GDI Technique

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of the reference clock, according to the workload of the EISC processor. The proposed self-calibration method and a phase detector with an auxiliary cha...

متن کامل

Design of Low voltage, Low Power and High Speed Logic Gates Using Modified GDI Technique

In low-voltage and low-power applications, optimization of several devices for speed and power is a significant issue. These issues can be overcome by incorporating Modified Gate Diffusion Input (Mod-GDI) technique. This technique has been adopted from Gate Diffusion Input (GDI). The Mod-GDI technique allows reducing power consumption, delay and area of digital circuits, while maintaining low c...

متن کامل

Low Power Circuits using Modified Gate Diffusion Input ( GDI )

Gate Diffusion Input (GDI) is a technique for designing low power circuits. This technique allows usage of less number of transistors as compared to CMOS logic. The basic GDI cell consists of only two transistors which are used to implement the basic logic functions. Because of less number of transistors, the switching is reduced and hence there will be a less power, delay and also reduced area...

متن کامل

Area Efficient Low Power Vedic Multiplier Design Using GDI Technique

Multipliers consume maximum amount of power during the partial product addition. For higher order multiplication, a huge number of adders are used to perform the partial product addition. Using compressor adders, that can add four, five , six or seven bits at a time, the number of full adders and half adders can be reduced and thus area and power consumed also gets reduced. These compressor add...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IJIREEICE

سال: 2015

ISSN: 2321-2004

DOI: 10.17148/ijireeice.2015.31017